Copper (Cu) is now becoming the standard material for connecting transistors in semiconductor devices. However, such devices cannot function properly if Cu diffuses into them. For instance, Cu reduces the resistance of the dielectric material insulating the interconnections. This leads to transistor threshold voltage shifts and reliability problems. For this reason, Cu must be confined inside diffusion barriers.
The copper-based formation of interconnects typically uses a so-called “damascene” process flow. This is a metal inlay process flow wherein, first trenches are etched in the inter-level dielectric layer (e.g. an oxide), then a thin layer is deposited on top of the inter-level dielectric layer in such a way as to cover the side walls of the trenches to prevent copper diffusion, next a seed layer is deposited to provide a conductive layer, which is required for the electroplating deposition process of the copper. Next, copper is electroplated. After electroplating, a chemical mechanical planarization step is performed to remove the excess copper and to polish the wafer. Then, a barrier layer is deposited to cover the top of the copper inlays, such that copper is fully encapsulated within the barrier material. Nowadays, both vias and trenches are simultaneously etched into the inter-layer dielectric and then simultaneously filled. This process is named dual-damascene.
CVD manganese (Mn) and manganese nitride (MnNx) are currently investigated as very promising barriers for the damascene/dual damascene formation of interconnects. For thicknesses down to 1 nm, their barrier properties and time dependent dielectric breakdown have been proven adequate on SiO2 patterned structures. Unfortunately, metal adherence and in particular copper adherence to these barriers is problematic.
Electrochemical metal plating on manganese or manganese nitride barriers is not an advantageous option to achieve the controlled filling of trenches having a width lower than 25 nm or lower than 15 nm because of the necessary presence of a relatively thick PVD Cu seed layer on top of the Mn barrier which would act as plating seed layer and more importantly protect the Mn barrier from dissolving in the plating bath. To the best of our knowledge, electroless metal deposition has never been demonstrated on Mn or MnNx barrier. For instance, electroless Cu deposition on Mn or MnNx was considered impossible due to the dissolution of Mn in the metallization bath. U.S. Pat. No. 8,569,165 discloses an interconnect structure for electronic circuits. In certain embodiments, manganese or manganese nitride is deposited via chemical vapor deposition or atomic layer deposition as a barrier layer against the diffusion of copper, oxygen and water. Next, a seed layer of Cu is formed, preferably by a conformal method such as CVD, ALD or PVD. Then the vias and trenches are filled by electrochemical deposition, followed by annealing. Examples show the filling of trenches having a width of about 30 nm. No electroless filling is disclosed which is not surprising since it was considered up to now as impossible. There is therefore still a need in the art for method overcoming one or more of the inconveniences mentioned above.